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220 ? may 2002 hm-65642/883 8k x 8 asynchronous cmos static ram features ? this circuit is processed in accordance to mil-std- 883 and is fully conformant under the provisions of paragraph 1.2.1. ? full cmos design ? six transistor memory cell ? low standby supply current . . . . . . . . . . . . . . . . 100 a ? low operating supply current. . . . . . . . . . . . . . . 20ma ? fast address access time . . . . . . . . . . . . . . . . . . 150ns ? low data retention supply voltage . . . . . . . . . . . 2.0v ? cmos/ttl compatible inputs/outputs ? jedec approved pinout ? equal cycle and access times ? no clocks or strobes required ? gated inputs - no pull-up or pull-down resistors required ? temperature range -55 o c to +125 o c ? easy microprocessor interfacing ? dual chip enable control description the hm-65642/883 is a cmos 8192 x 8-bit static random access memory. the pinout is the jedec 28 pin, 8-bit wide standard, which allows easy memory board layouts which accommodate a variety of industry standard rom, prom, eprom, eeprom and rams. the hm-65642/883 is ideally suited for use in microprocessor based systems. in particu- lar, interfacing with the intersil 80c86 and 80c88 micropro- cessors is simplified by the convenient output enable (g ) input. the hm-65642/883 is a full cmos ram which utilizes an array of six transistor (6t) memory cells for the most stable and lowest possible standby supply current over the full mili- tary temperature range. ordering information package temperature range 150ns/75 a 150ns/150 a 200ns/250 a pkg. no. cerdip -55 o c to +125 o c hm1-65642b/883 hm1-65642/883 hm1-65642c/883 f28.6 clcc -55 o c to +125 o c hm4-65642b/883 hm4-65642/883 - j32.a pinouts hm-65642/883 (cerdip) top view hm4-65642/883 (clcc) top view 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vcc e2 a8 a9 a11 a10 dq7 dq6 dq5 dq4 dq3 w g e1 5 6 7 8 11 10 9 13 12 27 28 29 26 25 24 23 22 21 3 2 1 4 32 31 30 16 17 18 19 20 14 15 a6 a5 a4 a3 a2 a1 a0 nc dq0 dq1 dq2 gnd nc dq3 dq4 dq5 vcc nc nc a7 a12 e2 w a8 a9 a11 g a10 e1 dq7 dq6 nc pin description a address input dq data input/output e1 chip enable e2 chip enable w write enable g output enable nc no connections gnd ground vcc power fn3004.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
221 absolute maximum rati ngs thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v input or output voltage applied for all grades. . . . . . . gnd -0.3v to vcc +0.3v typical derating factor . . . . . . . . . . . 5ma/mhz increase in iccop esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance (typical) ja jc cerdip package . . . . . . . . . . . . . . . . 45 o c/w 8 o c/w clcc package . . . . . . . . . . . . . . . . . . 55 o c/w 10 o c/w maximum storage temperature range . . . . . . . . .-65 o c to +150 o c maximum junction temperature. . . . . . . . . . . . . . . . . . . . . . +175 o c maximum lead temperature (soldering 10s). . . . . . . . . . . . +300 o c die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101,000 gates caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indica ted in the operational sections of this specification is not i mplied. operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range. . . . . . . . . . . . . . . . -55 o c to +125 o c input low voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.8v input high voltage. . . . . . . . . . . . . . . . . . . . . . . +2.2v to vcc +0.3v data retention supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.0v input rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns max. table 1. hm-65642/883 dc electrical performance specifications device guaranteed and 100% tested parameter symbol (note 1) conditions group a subgroups temperature limits units min max high level output voltage voh 1 vcc = 4.5v, io = -1.0ma 1, 2, 3 -55 o c t a +125 o c 2.4 - v low level output voltage vol vcc = 4.5v, io = 4.0ma 1, 2, 3 -55 o c t a +125 o c -0.4 v high impedance output leakage current iioz hm-65642b/883, hm-65642/883 vcc = 5.5v, g = 2.2v, vi/o = gnd or vcc 1, 2, 3 -55 o c t a +125 o c -1.0 +1.0 a hm-65642c/883 vcc = 5.5v, g = 2.2v, vi/o = gnd or vcc 1, 2, 3 -55 o c t a +125 o c -2.0 +2.0 a input leakage current ii hm-65642b/883, hm-65642/883 vcc = 5.5v, vi = gnd or vcc 1, 2, 3 -55 o c t a +125 o c -1.0 +1.0 a hm-65642c/883 vcc = 5.5v, vi = gnd or vcc 1, 2, 3 -55 o c t a +125 o c -2.0 +2.0 a standby supply current iccsb1 hm-65642b/883 vcc = 5.5v, e1 = vcc -0.3v or e2 = gnd +0.3v 1, 2, 3 -55 o c t a +125 o c - 100 a hm-65642/883 vcc = 5.5v, e1 = vcc -0.3v or e2 = gnd +0.3v 1, 2, 3 -55 o c t a +125 o c - 250 a hm-65642c/883 vcc = 5.5v, e1 = vcc -0.3v or e2 = gnd +0.3v 1, 2, 3 -55 o c t a +125 o c - 400 a standby supply current iccsb vcc = 5.5v, io = 0ma, e1 = 2.2v or e2 = 0.8v 1, 2, 3 -55 o c t a +125 o c -5ma enable supply current iccen vcc = 5.5v, io = 0ma, e1 =0.8v, e2 = 2.2v 1, 2, 3 -55 o c t a +125 o c -5ma operating supply current iccop vcc = 5.5v, g = 5.5v, (note 2), f = 1mhz, e1 = 0.8v, e2 = 2.2v 1, 2, 3 -55 o c t a +125 o c -20ma hm-65642/883
222 data retention supply current iccdr hm-65642b/883 vcc = 2.0v, e1 = vcc -0.3v or e2 = gnd +0.3v 1, 2, 3 -55 o c t a +125 o c -75 a hm-65642/883 vcc = 2.0v, e1 = vcc -0.3v or e2 = gnd +0.3v 1, 2, 3 -55 o c t a +125 o c - 150 a hm-65642c/883 vcc = 2.0v, e1 = vcc -0.3v or e2 = gnd +0.3v 1, 2, 3 -55 o c t a +125 o c - 250 a functional test ft vcc = 4.5v (note 3) 7, 8a, 8b -55 o c t a +125 o c -- - notes: 1. all voltages referenced to device gnd. 2. typical derating 5ma/mhz increase in iccop. 3. tested as follows: f = 2mhz, vih = 2.4v, vi l = 0.4v, ioh = -4.0ma, iol = 4.0ma, voh 1.5v, and vol 1.5v. table 1. hm-65642/883 dc electrical performance specifications (continued) device guaranteed and 100% tested parameter symbol (note 1) conditions group a subgroups temperature limits units min max table 2. hm-65642/883 ac electrical performance specifications parameters symbol (notes 1, 2) conditions group a sub- groups temperature limits units hm- 65642b/883 hm- 65642/883 hm- 65642c/883 min max min max min max read/write/ cycle time tavax vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c 150 - 150 - 200 - ns address access time tavqv vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c - 150 - 150 - 200 - output enable access time tglqv vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c - 70 - 70 - 70 ns chip enable access time te1lqv te2hqv vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c - 150 - 150 - 200 ns write recovery time twhax te1hax te2lax vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c10-10-10- ns chip enable to end-of-write te1le1h te2he2l vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c 90 - 90 - 120 - ns address setup time tavwl tave1l tave2h vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c0-0-0-ns write enable pulse width twlwh vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c 90 - 90 - 120 - ns data setup time tdvwh tdve1h tdve2l vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c60-60-80- ns hm-65642/883
223 data hold time twhdx vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c5-5-5-ns te1hdx vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c10-10-10- ns te2ldx vcc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c10-10-10- ns notes: 1. all voltages referenced to device gnd. 2. ac measurements assume transition time 5ns; input levels = 0.0v to 3.0v; timing reference levels = 1.5v; output load = 1ttl equivalent load and cl 50pf, for cl > 50pf, access times are derated 0.15ns/pf. table 3. hm-65642/883 electrical performance specifications parameter symbol conditions notes temperature limits min max units output high voltage voh2 vcc = 4.5v, io = -100 a1-55 o c t a +125 o c vcc -0.4 - v input capacitance cin vcc = open, f = 1mhz, all measurements refer- enced to device ground 1, 2 t a = +25 o c - 12 pf vcc = open, f = 1mhz, all measurements refer- enced to device ground 1, 3 t a = +25 o c - 10 pf i/o capacitance ci/o vcc = open, f = 1mhz, all measurements refer- enced to device ground 1, 2 t a = +25 o c - 14 pf vcc = 4.5v, vi/o = gnd or vcc, all measurements referenced to device ground 1, 3 t a = +25 o c - 12 pf write enable to output in high z twlqz vcc = 4.5v and 5.5v 1 -55 o c t a +125 o c - 50 ns write enable high to output on twhqx vcc = 4.5v and 5.5v 1 -55 o c t a +125 o c5 - ns chip enable to output on te1lqx te2hqx vcc = 4.5v and 5.5v 1 -55 o c t a +125 o c10 - ns output enable to output on tglqx vcc = 4.5v and 5.5v 1 -55 o c t a +125 o c5 - ns chip enable to output in high z te1hqz vcc = 4.5v and 5.5v 1 -55 o c t a +125 o c - 50 ns te2lqz 1 -55 o c t a +125 o c - 60 ns output disable to output in high z tghqz vcc = 4.5v and 5.5v 1 -55 o c t a +125 o c - 50 ns output hold from address change taxqx vcc = 4.5v and 5.5v 1 -55 o c t a +125 o c10 - ns notes: 1. the parameters listed in table 3 are cont rolled via design or process parameters and ar e not directly tested. these parameter s are char- acterized upon initial design release and upon design ch anges which would affect these characteristics. 2. applies to dip device types only. for design purposes cin = 6pf typical and ci/o = 7pf typical. 3. applies to lcc device types only. for design purposes cin = 4pf typical and ci/o = 5pf typical. table 2. hm-65642/883 ac electrical performance specifications (continued) parameters symbol (notes 1, 2) conditions group a sub- groups temperature limits units hm- 65642b/883 hm- 65642/883 hm- 65642c/883 min max min max min max hm-65642/883
224 table 4. applicable subgroups conformance groups groups method subgroups interim test 1 100%/5004 - interim test 100%/5004 1, 7, 9 pda 100%/5004 1 final test 1 100%/5004 2, 3, 8a, 8b, 10, 11 group a samples/5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 groups c and d samples/5005 1, 7, 9 hm-65642/883
225 low voltage data retention intersil cmos rams are designed with battery backup in mind. data retention voltage and supply current are guaran- teed over the operating temperature range. the following rules ensure data retention: 1. the ram must be kept disabled during data retention. this is ac- complished by holding the e2 pin between -0.3v and gnd. 2. during power-up and power-down transitions, e2 must be held between -0.3v and 10% of vcc. 3. the ram can begin operating one tavax after vcc reaches the minimum operating voltage of 4.5v. read cycles figure 2. read cycle i: w , e2 high; g , e1 low 4.5v vcc vih e2 vccor gnd data retention mode tavax figure 1. data retention a address 1 q tavax tavqv taxqx address 2 data 1 data 2 hm-65642/883
226 figure 3. read cycle ii: w high read cycles tavax tavqv te1lqv te1lqx te1hqz te2lqz te2hqv te2hqx tglqv tglqx tghqz a e2 g q e1 hm-65642/883
227 write cycles figure 4. write cycle i: late write figure 5. write cycle ii: early write - controlled by e1 tavax twlwh twhax twhdx tdvwh a w e2 d q e1 twhqx tavwl twlqz tavax te1le1h tdve1h a w e2 d e1 tave1l te1hdx te1hax hm-65642/883
228 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com figure 6. write cycle iii: early write - controlled by e2 write cycles tavax te2he2l tdve2l a w e2 d e1 tave2h te2lax te2ldx hm-65642/883
229 test circuit burn-in circuits hm-65642/883 cerdip top view notes: f0 = 100khz 10%. all resistors 47k ? 5%. c = 0.01 f min. vcc = 5.5v 0.5v. vih = 4.5v 10%. vil = -0.2v to +0.4v. hm-65642/883 clcc top view notes: f0 = 100khz 10%. c = 0.01 f min. vcc = 5.5v 0.5v. vih = 4.5v 10%. vil = -0.2v to +0.4v. dut 1.5v iol ioh + - (note 1) c l equivalent circuit note: 1. test head capacitance. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd c a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd nc f15 f10 f9 f8 f7 f6 f5 f4 f3 f2 f2 f2 f1 f16 f11 f12 f13 f0 f0 f2 f2 f2 f14 f2 f2 vcc a8 a9 a11 a10 dq7 dq6 dq5 dq4 dq3 g e2 w e1 dq1 dq2 gnd nc dq4 dq5 a6 a5 a4 a3 a2 a1 a0 nc f2 f2 f2 f2 f2 f2 dq3 14 15 16 17 18 19 20 f9 f8 f7 f6 f5 f4 f3 dq0 5 6 7 8 11 9 13 12 10 a8 a9 a11 nc g a10 dq7 27 28 29 26 25 24 23 22 21 f11 f12 f14 f0 f13 f0 f2 f2 e2 w vcc nc nc a12 a7 f10 f15 f1 f16 3 2 1 4 32 31 30 c vcc dq6 e1
230 die characteristics die dimensions: 274.0 x 302.8 x 19 1mils metallization: type: si - al thickness: 11k ? 2k ? glassivation: type: sio 2 thickness: 8k ? 1k ? worst case current density: 0.9 x 10 5 a/cm 2 metallization mask layout hm-65642/883 a8 a7 a12 vcc w e2 a8 a9 a11 g a10 e1 dq7 dq6 dq5 dq4 dq3 gnd dq2 dq1 dq0 a0 a1 a2 a3 a4 a5 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com

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